The present invention relates to wireless communication systems and, more particularly, to a method of multichip synchronization in a remote radio head.
FIG. 1 shows a topology of a multichip remote radio head (RRH) environment of a transmission node 100 in a wireless communication network. The transmission node 100 includes at least two digital front-end devices 102 and 104 controlled by a system controller 106. Each of the digital front-end devices 102 and 104 respectively communicates with one of radio frequency interface chips (RFICs) 108 and 110 using the JESD204B protocol, which is a serial protocol. A RFIC is a device that has an analog to digital converter (ADC), a digital to analog converter (DAC) and an interface to a radio frequency physical antenna (RF PA), such as antennas 112 and 114. The JESD204B protocol requires a plurality of functional clocks provided by the digital front-end devices 102 and 104 indicating different timing boundaries, such as a character clock, a bi-character clock, a quad-character clock depending on a size of the bus implemented in JESD204B transports, and a programmable generated clock. The plurality of functional clocks are generated by dividing a phase locked clock using different division ratios dictated by serial line rates. The phase locked clock is generated from a device clock of each front-end device 102, 104 by a phase locked loop (PLL) (not shown). It is required that all of the functional clocks have a positive edge aligned at a functional start of the transports, which happens after booting or reset, or upon a re-synchronization request 116. The multichip resynchronization is required to be completed within one radio frame with a length of 10 ms.
The topology further requires stringent sampling certainty of a system reference signal SYSREF 118, which dictates the radio frame timing boundaries to the digital front-end devices 102 and 104. The SYSREF 118 is sampled by a device clock 120 of the digital front-end device 102, 104. Since JESD204B works on a phase locked clock 122 generated by the PLL in each digital front-end device 102, 104, the SYSREF sampling is required to be aligned with both the device clock 120 and the phase locked clock 122. However, as shown in FIG. 2, PLL jitter moves the edge of the phase locked clock 122 either behind or ahead of the edge of an ideal phase locked clock PLL_CLK, as shown by PLL_CLK′ 124 and PLL_CLK″ 126, which results in a high probability of either a hold or setup violation.
It is therefore necessary to align all of the functional clocks with the device clock upon a reset or system re-synchronization request, or PLL re-locking, and ensure deterministic sampling of the system reference signal.